讲解U6 CERT TEST全过(图文)

发布时间：2010-09-08 02:18:25 作者：佚名

U6的40G盘。好多红绿块。几乎全盘都是。于是维修的过程。顺便写了个教程。希望对大家有帮助。关于什么是CERT大家可以搜索论坛的精华帖子。要做U6的CERT TEST必须有CERT ROM。CERT ROM见附件。把含有CERT的电路板换到待修盘的盘体上。然后把电源和CO

OK，硬盘的CERT TEST已经开始了。我们接下来所需要做的就是等待，我把机器关了，把硬盘接在AT电源上。俺去睡觉也。一般来说，我们只需要一直等到硬盘停转就可以了，工厂指定执行CERT TEST的标准时间是72个小时，超过这个时间限度的话，说明该驱动器存在严重缺陷，将不适合出厂了。
第二天一大早醒来。摸摸盘体。已经停转了。

然后我把原盘的电路板换回去。通电。终端窗口显示如下提示：

Intf tsk rst 1024k x 16 buffer detected

Ref 0183 - Hd Msk 0A00 - Switch to full int. (磁头已经复位，准备开始工作)
Ready (准备就绪)
ATRst
ROM&RAMHeadMapDiff
U6 - ST340810A(S),03.39
Valid CSPT - Rev FF.07.03.21
Valid RWF - Rev D0.06

Valid VBPI - Rev 00.1A
Valid OVLY - Rev 03.39.77
Begin Test 3F
OkEnd Test 3F

Intf tsk rst 1024k x 16 buffer detected

Valid VBPI - Rev 00.1A
Valid OVLY - Rev 03.39.77
Begin Test 3F
OkEnd Test 3F (这里将会停止在3F，3F在U6流程中的含义是AT Rom Flashing。这里我们必须更换回AT ROM了，即把原配的电路板安装回来)

T>N40 (这里我们手动输入N40，意思是从AGE=40继续执行CERT TEST测试。然后按CTRL+T)

Hd Msk 0A00 - Switch to full int.
Ready
T>Begin Test 40 (开跑了)
Goodcopy=04
KEY 02h Valid

OkEnd Test 40
Begin Test 4A
All Hds 0-1, All Cyls 007C-D993, 2EE0 mS cmd timeout
All Hds 0-1, All Cyls 007C-D993, 2EE0 mS cmd timeout
All Hds 0-1, All Cyls 007C-07D0, 2EE0 mS cmd timeout
LpRcov=1 TA=1 ChTwk=1 OTRd=1 EarlyRd=0 Splash=1 SDly\Rload=1 VCOCal=1
ForcedSync=1 Burnish=1 SrvoTrsh=1 RunOut=1 MaxECC=1 ECC2=1 ECC1=1 ECC0=1
Data=67 Write=80 GlobalData=00 RetryMode=00

Rbit Hard Firm Soft OTF Raw Rhdr Wbit Whrd Wrty Whdr
Limit 10.2 10.2 9.5 8.0 6.0 4.0 0.0 9.2 9.2 6.5 0.0
Hd 0 10.4 10.4 10.4 10.4 9.2 6.6 10.4 10.2 10.2 9.7 10.2
Hd 1 10.4 10.4 10.4 10.4 8.9 7.1 10.4 10.2 10.2 10.2 10.2
No entries in Log
--- Retry Counters ---
Hd0
0000: 000f 0000 0000 0000 0000 0000 0000 0000
0008: 0000 0000 0000 0000 0000 0000 0000 0000
0010: 0000 0000 0000 0000 0000 0000 0000 0000
0018: 0000 0000 0000 0000 0000 0000 0000 0000
0020: 0000 0000 0000 0000 0000 0000 0000 0000
0028: 0000 0000 0000 0000 0000 0000 0000 0000
0030: 0000 0000 0000
Hd1
0000: 001e 0000 0000 0000 0000 0000 0000 0000
0008: 0000 0000 0000 0000 0000 0000 0000 0000
0010: 0000 0000 0000 0000 0000 0000 0000 0000
0018: 0000 0000 0000 0000 0000 0000 0000 0000
0020: 0000 0000 0000 0000 0000 0000 0000 0000
0028: 0000 0000 0000 0000 0000 0000 0000 0000
0030: 0000 0000 0000
Hd2
0000: 0000 0000 0000 0000 0000 0000 0000 0000
0008: 0000 0000 0000 0000 0000 0000 0000 0000
0010: 0000 0000 0000 0000 0000 0000 0000 0000
0018: 0000 0000 0000 0000 0000 0000 0000 0000
0020: 0000 0000 0000 0000 0000 0000 0000 0000
0028: 0000 0000 0000 0000 0000 0000 0000 0000
0030: 0000 0000 0000
Hd3
0000: 0000 0000 0000 0000 0000 0000 0000 0000
0008: 0000 0000 0000 0000 0000 0000 0000 0000
0010: 0000 0000 0000 0000 0000 0000 0000 0000
0018: 0000 0000 0000 0000 0000 0000 0000 0000
0020: 0000 0000 0000 0000 0000 0000 0000 0000
0028: 0000 0000 0000 0000 0000 0000 0000 0000
0030: 0000 0000 0000
OkEnd Test 4A
Begin Test 49
Tm 90
Rmr
H00 1518
H01 1450
VGA
0200.00=0078
0200.01=0068
OkEnd Test 49
Begin Test 48
Hd 0
Surf 0, Rnd cyls 007C-D993, 2EE0 mS cmd timeout
Surf 0, Rnd cyls 007C-D993, 2EE0 mS cmd timeout
Surf 0, Rnd cyls 007C-D993, 2EE0 mS cmd timeout

Pick current = 0000 DAC bits.

DAC offset = -01A6 DAC bits.
Out In
CYL = 045E Bias = 0067 Bias = 0067
CYL = 0C5E Bias = 00CE Bias = 00B7
CYL = 145E Bias = 00BD Bias = 00AF
CYL = 1C5E Bias = 00B7 Bias = 00A3
CYL = 245E Bias = 00A5 Bias = 0098
CYL = 2C5E Bias = 00A6 Bias = 008A
CYL = 345E Bias = 00A5 Bias = 0088
CYL = 3C5E Bias = 0097 Bias = 0081
CYL = 445E Bias = 007A Bias = 0078
CYL = 4C5E Bias = 0080 Bias = 006D
CYL = 545E Bias = 007F Bias = 006D
CYL = 5C5E Bias = 0067 Bias = 0062
CYL = 645E Bias = 005D Bias = 0057
CYL = 6C5E Bias = 0066 Bias = 0055
CYL = 745E Bias = 005B Bias = 0048
CYL = 7C5E Bias = 004B Bias = 0044
CYL = 845E Bias = 0046 Bias = 0041
CYL = 8C5E Bias = 0040 Bias = 0038
CYL = 945E Bias = 0043 Bias = 0035
CYL = 9C5E Bias = 0036 Bias = 0030
CYL = A45E Bias = 0034 Bias = 0026
CYL = AC5E Bias = 0027 Bias = 001E
CYL = B45E Bias = 002D Bias = 001A
CYL = BC5E Bias = 0019 Bias = 0012
CYL = C45E Bias = 0014 Bias = 000D
CYL = CC5E Bias = 0011 Bias = 000E
CYL = D45E Bias = 0010 Bias = 0011
CYL = D758 Bias = 000C Bias = -003F
SkCnt = 4.4 SkErr = 0.0
Hd 1
Surf 1, Rnd cyls 007C-D993, 2EE0 mS cmd timeout
Surf 1, Rnd cyls 007C-D993, 2EE0 mS cmd timeout
Surf 1, Rnd cyls 007C-D993, 2EE0 mS cmd timeout

Pick current = 0000 DAC bits.

DAC offset = -01A6 DAC bits.
Out In
CYL = 045E Bias = 0067 Bias = 0063
CYL = 0C5E Bias = 0067 Bias = 00B1
CYL = 145E Bias = 0067 Bias = 0098
CYL = 1C5E Bias = 00B7 Bias = 009A
CYL = 245E Bias = 00B7 Bias = 0091
CYL = 2C5E Bias = 00A5 Bias = 0082
CYL = 345E Bias = 00A5 Bias = 0080
CYL = 3C5E Bias = 0097 Bias = 007A
CYL = 445E Bias = 007A Bias = 007A
CYL = 4C5E Bias = 007A Bias = 0060
CYL = 545E Bias = 007F Bias = 0060
CYL = 5C5E Bias = 007F Bias = 0055
CYL = 645E Bias = 007F Bias = 0046
CYL = 6C5E Bias = 0066 Bias = 0046
CYL = 745E Bias = 0066 Bias = 003C
CYL = 7C5E Bias = 004B Bias = 003C
CYL = 845E Bias = 004B Bias = 0030
CYL = 8C5E Bias = 0040 Bias = 0027
CYL = 945E Bias = 0043 Bias = 0034
CYL = 9C5E Bias = 0036 Bias = 0034
CYL = A45E Bias = 0034 Bias = 001B
CYL = AC5E Bias = 0034 Bias = 000C
CYL = B45E Bias = 002D Bias = 0014
CYL = BC5E Bias = 0019 Bias = 0014
CYL = C45E Bias = 0014 Bias = 000E
CYL = CC5E Bias = 0011 Bias = -0040
CYL = D45E Bias = 0010 Bias = -0040
CYL = D758 Bias = 000C Bias = -0040
SkCnt = 4.4 SkErr = 0.0
OkEnd Test 48
Begin Test 42
LpRcov=1 TA=0 ChTwk=1 OTRd=1 EarlyRd=1 Splash=1 SDly\Rload=1 VCOCal=1
ForcedSync=1 Burnish=0 SrvoTrsh=0 RunOut=1 MaxECC=0 ECC2=0 ECC1=1 ECC0=1
Data=34 Write=80 GlobalData=00 RetryMode=00
Zone 1
All Hds 0-1, All Cyls 007C-07D0, 2EE0 mS cmd timeout

Rbit Hard Firm Soft OTF Raw Rhdr Wbit Whrd Wrty Whdr
Limit
Hd 0 9.8 9.8 9.8 9.8 9.8 7.6 9.8 9.8 9.8 9.8 9.8
Hd 1 9.8 9.8 9.8 9.8 9.8 8.3 9.8 9.8 9.8 9.8 9.8
No entries in Log
Zone 2
All Hds 0-1, All Cyls 07D1-1D4C, 2EE0 mS cmd timeout

Rbit Hard Firm Soft OTF Raw Rhdr Wbit Whrd Wrty Whdr
Limit
Hd 0 10.2 10.2 10.2 10.2 10.2 8.3 10.2 10.2 10.2 10.2 10.2
Hd 1 10.2 10.2 10.2 10.2 10.2 7.7 10.2 10.2 10.2 10.2 10.2
No entries in Log
Zone 3
All Hds 0-1, All Cyls 1D4D-32FA, 2EE0 mS cmd timeout

Rbit Hard Firm Soft OTF Raw Rhdr Wbit Whrd Wrty Whdr
Limit
Hd 0 10.2 10.2 10.2 10.2 10.2 7.7 10.2 10.2 10.2 10.2 10.2
Hd 1 10.2 10.2 10.2 10.2 10.2 7.2 10.2 10.2 10.2 10.2 10.2
No entries in Log
Zone 4
All Hds 0-1, All Cyls 32FB-4876, 2EE0 mS cmd timeout

Rbit Hard Firm Soft OTF Raw Rhdr Wbit Whrd Wrty Whdr
Limit
Hd 0 10.2 10.2 10.2 10.2 10.2 8.1 10.2 10.2 10.2 10.2 10.2
Hd 1 10.2 10.2 10.2 10.2 10.2 7.8 10.2 10.2 10.2 10.2 10.2
No entries in Log
Zone 5
All Hds 0-1, All Cyls 4877-59D8, 2EE0 mS cmd timeout

Rbit Hard Firm Soft OTF Raw Rhdr Wbit Whrd Wrty Whdr
Limit
Hd 0 10.1 10.1 10.1 10.1 10.1 7.4 10.1 10.1 10.1 10.1 10.1
Hd 1 10.1 10.1 10.1 10.1 10.1 7.7 10.1 10.1 10.1 10.1 10.1
No entries in Log
Zone 6
All Hds 0-1, All Cyls 59D9-6978, 2EE0 mS cmd timeout

Rbit Hard Firm Soft OTF Raw Rhdr Wbit Whrd Wrty Whdr
Limit
Hd 0 10.0 10.0 10.0 10.0 10.0 7.4 10.0 10.0 10.0 10.0 10.0
Hd 1 10.0 10.0 10.0 10.0 10.0 7.6 10.0 10.0 10.0 10.0 10.0
No entries in Log
Zone 7
All Hds 0-1, All Cyls 6979-7850, 2EE0 mS cmd timeout

Rbit Hard Firm Soft OTF Raw Rhdr Wbit Whrd Wrty Whdr
Limit
Hd 0 10.0 10.0 10.0 10.0 10.0 7.0 10.0 10.0 10.0 10.0 10.0
Hd 1 10.0 10.0 10.0 10.0 9.7 7.2 10.0 10.0 10.0 10.0 10.0
No entries in Log
Zone 8
All Hds 0-1, All Cyls 7851-87F0, 2EE0 mS cmd timeout

Rbit Hard Firm Soft OTF Raw Rhdr Wbit Whrd Wrty Whdr
Limit
Hd 0 10.0 10.0 10.0 10.0 10.0 7.3 10.0 10.0 10.0 10.0 10.0
Hd 1 10.0 10.0 10.0 10.0 10.0 6.9 10.0 10.0 10.0 10.0 10.0
No entries in Log
Zone 9
All Hds 0-1, All Cyls 87F1-96C8, 2EE0 mS cmd timeout

Rbit Hard Firm Soft OTF Raw Rhdr Wbit Whrd Wrty Whdr
Limit
Hd 0 9.9 9.9 9.9 9.9 9.9 7.2 9.9 9.9 9.9 9.9 9.9
Hd 1 9.9 9.9 9.9 9.9 9.9 6.8 9.9 9.9 9.9 9.9 9.9
No entries in Log
Zone A
All Hds 0-1, All Cyls 96C9-A730, 2EE0 mS cmd timeout

Rbit Hard Firm Soft OTF Raw Rhdr Wbit Whrd Wrty Whdr
Limit
Hd 0 10.0 10.0 10.0 10.0 10.0 7.2 10.0 10.0 10.0 10.0 10.0
Hd 1 10.0 10.0 10.0 10.0 10.0 7.0 10.0 10.0 10.0 10.0 10.0
No entries in Log
Zone B
All Hds 0-1, All Cyls A731-B63A, 2EE0 mS cmd timeout

Rbit Hard Firm Soft OTF Raw Rhdr Wbit Whrd Wrty Whdr
Limit
Hd 0 9.9 9.9 9.9 9.9 9.9 6.7 9.9 9.9 9.9 9.9 9.9
Hd 1 9.9 9.9 9.9 9.9 9.6 6.5 9.9 9.9 9.9 9.6 9.9
No entries in Log
Zone C
All Hds 0-1, All Cyls B63B-CA58, 2EE0 mS cmd timeout

Rbit Hard Firm Soft OTF Raw Rhdr Wbit Whrd Wrty Whdr
Limit
Hd 0 10.0 10.0 10.0 10.0 10.0 7.2 10.0 10.0 10.0 10.0 10.0
Hd 1 10.0 10.0 10.0 10.0 10.0 6.9 10.0 10.0 10.0 10.0 10.0
No entries in Log
Zone D
All Hds 0-1, All Cyls CA59-D993, 2EE0 mS cmd timeout

Rbit Hard Firm Soft OTF Raw Rhdr Wbit Whrd Wrty Whdr
Limit
Hd 0 9.9 9.9 9.9 9.9 9.9 7.7 9.9 9.9 9.9 9.9 9.9
Hd 1 9.9 9.9 9.9 9.9 9.9 7.4 9.9 9.9 9.9 9.9 9.9
No entries in Log

Rbit Hard Firm Soft OTF Raw Rhdr Wbit Whrd Wrty Whdr
Limit 10.2 10.2 8.8 8.5 6.0 5.5 0.0 9.2 9.2 6.5 0.0
Hd 0 11.1 11.1 11.1 11.1 11.1 7.2 11.1 11.1 11.1 11.1 11.1
Hd 1 11.1 11.1 11.1 11.1 10.2 7.1 11.1 11.1 11.1 10.8 11.1
--- Retry Counters ---
Hd0
0000: 000f 0000 0000 0000 0000 0000 0000 0000
0008: 0000 0000 0000 0000 0000 0000 0000 0000
0010: 0000 0000 0000 0000 0000 0000 0000 0000
0018: 0000 0000 0000 0000 0000 0000 0000 0000
0020: 0000 0000 0000 0000 0000 0000 0000 0000
0028: 0000 0000 0000 0000 0000 0000 0000 0000
0030: 0000 0000 0000
Hd1
0000: 0025 0000 0000 0000 0000 0000 0000 0000
0008: 0000 0000 0000 0000 0000 0000 0000 0000
0010: 0000 0000 0000 0000 0000 0000 0000 0000
0018: 0000 0000 0000 0000 0000 0000 0000 0000
0020: 0000 0000 0000 0000 0000 0000 0000 0000
0028: 0000 0000 0000 0000 0000 0000 0000 0000
0030: 0000 0000 0000
Hd2
0000: 0000 0000 0000 0000 0000 0000 0000 0000
0008: 0000 0000 0000 0000 0000 0000 0000 0000
0010: 0000 0000 0000 0000 0000 0000 0000 0000
0018: 0000 0000 0000 0000 0000 0000 0000 0000
0020: 0000 0000 0000 0000 0000 0000 0000 0000
0028: 0000 0000 0000 0000 0000 0000 0000 0000
0030: 0000 0000 0000
Hd3
0000: 0000 0000 0000 0000 0000 0000 0000 0000
0008: 0000 0000 0000 0000 0000 0000 0000 0000
0010: 0000 0000 0000 0000 0000 0000 0000 0000
0018: 0000 0000 0000 0000 0000 0000 0000 0000
0020: 0000 0000 0000 0000 0000 0000 0000 0000
0028: 0000 0000 0000 0000 0000 0000 0000 0000
0030: 0000 0000 0000
OkEnd Test 42
Begin Test 43
Single trk - Hd 0, 2EE0 mS cmd timeout
LpRcov=0 TA=0 ChTwk=1 OTRd=0 EarlyRd=0 Splash=1 SDly\Rload=1 VCOCal=1
ForcedSync=1 Burnish=1 SrvoTrsh=1 RunOut=1 MaxECC=0 ECC2=0 ECC1=0 ECC0=0
Data=67 Write=80 GlobalData=00 RetryMode=00
LpRcov=0 TA=0 ChTwk=0 OTRd=0 EarlyRd=0 Splash=0 SDly\Rload=0 VCOCal=0
ForcedSync=0 Burnish=0 SrvoTrsh=0 RunOut=0 MaxECC=0 ECC2=0 ECC1=1 ECC0=1
Data=67 Write=80 GlobalData=00 RetryMode=00
Expected
0001 Entries:
_____Head____0_____ _____Head____1_____ _____Head____2_____ _____Head____3_____
43 0100.000) 000( 001

LpRcov=0 TA=0 ChTwk=0 OTRd=0 EarlyRd=0 Splash=0 SDly\Rload=0 VCOCal=0
ForcedSync=0 Burnish=0 SrvoTrsh=0 RunOut=0 MaxECC=1 ECC2=1 ECC1=1 ECC0=1
Data=67 Write=80 GlobalData=00 RetryMode=00
No entries in Log
LpRcov=0 TA=0 ChTwk=0 OTRd=0 EarlyRd=0 Splash=0 SDly\Rload=0 VCOCal=0
ForcedSync=0 Burnish=0 SrvoTrsh=0 RunOut=0 MaxECC=1 ECC2=1 ECC1=1 ECC0=1
Data=67 Write=80 GlobalData=00 RetryMode=00
Expected
0001 Entries:
_____Head____0_____ _____Head____1_____ _____Head____2_____ _____Head____3_____
43 0100.000) 000( 001

LpRcov=0 TA=0 ChTwk=0 OTRd=0 EarlyRd=0 Splash=0 SDly\Rload=0 VCOCal=0
ForcedSync=0 Burnish=0 SrvoTrsh=0 RunOut=0 MaxECC=0 ECC2=0 ECC1=1 ECC0=1
Data=67 Write=80 GlobalData=00 RetryMode=00
Expected
0001 Entries:
_____Head____0_____ _____Head____1_____ _____Head____2_____ _____Head____3_____
43 D000.000) 000( 001

OkEnd Test 43
Begin Test 4E
Log4E - Cert Summary: Rom -,03.39.177
Ovly - 03.39.77
(SN: 5FB5SAFT)
.PW

TLog 04 - Health 0000 - Time = 00:01:38 - Sns = 00000000

TLog 07 - Health 0000 - Time = 00:00:00 - Sns = 00000000

TLog 0C - Health 0000 - Time = 00:14:12 - Sns = 00000000

TLog 10 - Health 0000 - Time = 00:12:56 - Sns = 00000000

TLog 15 - Health 0000 - Time = 00:04:48 - Sns = 00000000

TLog 1D - Health 0000 - Time = 00:14:44 - Sns = 00000000

TLog 12 - Health 0000 - Time = 00:01:22 - Sns = 00000000

TLog 11 - Health 0000 - Time = 00:05:20 - Sns = 00000000

TLog 16 - Health 0000 - Time = 00:33:46 - Sns = 00000000

TLog 19 - Health 0000 - Time = 00:03:10 - Sns = 00000000

TLog 18 - Health 0000 - Time = 00:01:06 - Sns = 00000000

TLog 1A - Health 0000 - Time = 00:11:40 - Sns = 00000000

TLog 13 - Health 0000 - Time = 00:13:16 - Sns = 00000000

TLog 1B - Health 0000 - Time = 00:11:40 - Sns = 00000000

TLog 1C - Health 0000 - Time = 00:13:42 - Sns = 00000000

TLog 1E - Health 0000 - Time = 00:03:10 - Sns = 00000000

TLog 1F - Health 0000 - Time = 00:00:12 - Sns = 00000000

TLog 23 - Health 0000 - Time = 00:16:24 - Sns = 00000000

TLog 08 - Health 0000 - Time = 07:12:46 - Sns = 00000000

TLog 33 - Health 0000 - Time = 00:00:14 - Sns = 00000000

TLog 06 - Health 0000 - Time = 00:00:06 - Sns = 00000000

TLog 0B - Health 0000 - Time = 00:00:46 - Sns = 00000000

TLog 20 - Health 0000 - Time = 00:47:04 - Sns = 00000000

TLog 30 - Health 0000 - Time = 00:00:04 - Sns = 00000000

TLog 0E - Health 0000 - Time = 00:00:12 - Sns = 00000000

TLog 39 - Health 0000 - Time = 03:11:12 - Sns = 00000000

TLog 34 - Health 0000 - Time = 00:00:14 - Sns = 00000000

TLog 31 - Health 0000 - Time = 00:57:52 - Sns = 00000000

TLog 35 - Health 0000 - Time = 00:00:12 - Sns = 00000000

TLog 3C - Health 0000 - Time = 00:00:04 - Sns = 00000000

TLog 37 - Health 0000 - Time = 00:16:36 - Sns = 00000000

TLog 3E - Health 0000 - Time = 00:00:08 - Sns = 00000000

TLog 6F - Health 0000 - Time = 00:00:08 - Sns = 00000000

TLog 22 - Health 0000 - Time = 00:00:02 - Sns = 00000000

TLog 21 - Health 0000 - Time = 00:03:50 - Sns = 00000000

TLog 14 - Health 0000 - Time = 00:00:58 - Sns = 00000000

TLog 25 - Health 0000 - Time = 00:02:54 - Sns = 00000000

TLog 70 - Health 0000 - Time = 00:47:04 - Sns = 00000000

TLog 6D - Health 0000 - Time = 00:12:40 - Sns = 00000000

TLog 40 - Health 0000 - Time = 00:00:02 - Sns = 00000000

TLog 4A - Health 0000 - Time = 00:08:16 - Sns = 00000000

TLog 49 - Health 0000 - Time = 00:00:00 - Sns = 00000000

TLog 48 - Health 0000 - Time = 00:23:58 - Sns = 00000000

TLog 42 - Health 0000 - Time = 01:08:38 - Sns = 00000000

TLog 43 - Health 0000 - Time = 00:00:18 - Sns = 00000000
Total Time = 17:59:24 (CERT测试总共花了17小时59分24秒)
OkEnd Test 50 (CERT TEST成功结束了)

T> (这时硬盘已经停转了。我们可以断电取下来了)

做完后该硬盘在MHDD中测试。没有一个绿块。爽

CERT ROM通常就2个。339的ROM可以做319 339 399版本的盘。333的ROM可以做331 334 533的盘。

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